熊正权,窦筠雯,陈颖,高能,黄银,朱旻昊,冯雪.面向超薄硅晶圆精密磨削工艺的内部残余应力分析[J].表面技术,2025,54(2):161-172.
XIONG Zhengquan,DOU Junwen,CHEN Ying,GAO Neng,HUANG Yin,ZHU Minhao,FENG Xue.#$NPAnalysis of Internal Residual Stress for Precision Grinding Process of Ultra-thin Silicon Wafers[J].Surface Technology,2025,54(2):161-172 |
| 面向超薄硅晶圆精密磨削工艺的内部残余应力分析 |
| #$NPAnalysis of Internal Residual Stress for Precision Grinding Process of Ultra-thin Silicon Wafers |
| 投稿时间：2024-04-25 修订日期：2024-05-16 |
| DOI：10.16490/j.cnki.issn.1001-3660.2025.02.013 |
| 中文关键词: 硅晶圆 超薄 精密磨削 内部残余应力 有限元仿真 显微拉曼实验 |
| 英文关键词:silicon wafer ultra-thin precision grinding internal residual stress finite element simulation micro-Raman experiment |
| 基金项目:国家自然科学基金(11972027，U20A6001);西南交通大学新型交叉学科培育基金项目(2682022JX001) |
| 作者 | 单位 |
| 熊正权 | 西南交通大学 材料科学与工程学院 材料先进技术教育部重点实验室机械工程学院 摩擦学研究所，成都 610031 |
| 窦筠雯 | 西南交通大学 材料科学与工程学院 材料先进技术教育部重点实验室机械工程学院 摩擦学研究所，成都 610031 |
| 陈颖 | 清华大学 柔性电子技术实验室，航天航空学院，北京 100084;浙江清华柔性电子技术研究院，浙江 嘉兴 314000 |
| 高能 | 电子科技大学 材料与能源学院，成都 610054 |
| 黄银 | 西南交通大学 材料科学与工程学院 材料先进技术教育部重点实验室机械工程学院 摩擦学研究所，成都 610031 |
| 朱旻昊 | 西南交通大学 材料科学与工程学院 材料先进技术教育部重点实验室机械工程学院 摩擦学研究所，成都 610031 |
| 冯雪 | 清华大学 柔性电子技术实验室，航天航空学院，北京 100084;浙江清华柔性电子技术研究院，浙江 嘉兴 314000 |
|
| Author | Institution |
| XIONG Zhengquan | Key Laboratory of Advanced Technologies of Materials Ministry of Education, School of Materials Science and Engineering,Tribology Research Institute,School of Mechanical Engineering, Southwest Jiaotong University, Chengdu 610031, China |
| DOU Junwen | Key Laboratory of Advanced Technologies of Materials Ministry of Education, School of Materials Science and Engineering,Tribology Research Institute,School of Mechanical Engineering, Southwest Jiaotong University, Chengdu 610031, China |
| CHEN Ying | Center for Flexible Electronics Technology,School of Aerospace Engineering, Tsinghua University, Beijing 100084, China;Institute of Flexible Electronics Technology of THU, Zhejiang Jiaxing 314000, China |
| GAO Neng | School of Materials & Energy, University of Electronic Science & Technology of China, Chengdu 610054, China |
| HUANG Yin | Key Laboratory of Advanced Technologies of Materials Ministry of Education, School of Materials Science and Engineering,Tribology Research Institute,School of Mechanical Engineering, Southwest Jiaotong University, Chengdu 610031, China |
| ZHU Minhao | Key Laboratory of Advanced Technologies of Materials Ministry of Education, School of Materials Science and Engineering,Tribology Research Institute,School of Mechanical Engineering, Southwest Jiaotong University, Chengdu 610031, China |
| FENG Xue | Center for Flexible Electronics Technology,School of Aerospace Engineering, Tsinghua University, Beijing 100084, China;Institute of Flexible Electronics Technology of THU, Zhejiang Jiaxing 314000, China |
|
| 摘要点击次数: |
| 全文下载次数: |
| 中文摘要: |
| 目的 硅基集成电路的超薄化(通常厚度≤50 µm)是高性能集成器件实现柔性化的关键，同时也满足了器件先进封装的需求。背面精密磨削是低成本、大规模制造超薄硅基集成电路的重要技术路径。然而，随着厚度的降低，本征硬脆的硅基器件的机械强度急剧下降，磨削的难度也极大增加。此外，当器件的厚度接近甚至低于有源层厚度(约为15 μm)时，磨削过程中产生的缺陷和内部残余应力将严重影响超薄器件的性能和良品率。因此，控制磨削过程的缺陷和内部残余应力是突破超薄柔性硅基集成电路制备技术的关键，非常有必要深入分析超薄硅晶圆精密磨削产生的内部残余应力，建立起工艺参数与内部残余应力之间的定量关系。方法 针对精密磨削工艺，基于磨轮与硅晶圆的几何运动学关系，将磨轮进给率对磨削过程的影响转变为对等效磨削深度的影响，建立了硅晶圆在单颗磨粒单次和多颗磨粒多次磨削下的有限元局部模型，探讨了工艺参数(磨轮转速、磨轮进给率、磨粒尺寸)、磨粒数量和磨削次数对磨削后的表面质量和内部残余应力的影响，开展了12英寸硅晶圆的自旋转精密磨削实验验证仿真。结果 硅晶圆精密磨削后的内部残余应力主要集中于距离硅片表面约50 nm处，并沿深度方向快速减小。降低磨轮进给率和减小磨粒尺寸可以有效降低内部残余应力，提高表面质量。使硅片磨削后的表面及内部区域近似处于等双轴压缩应力状态，当磨轮进给率为0.5、0.35和0.2 mm/s时，通过激光共聚焦显微拉曼光谱仪测得残余应力分别为(−185±33)、(−216±25)和(283±41) MPa，多颗磨粒多次磨削有限元仿真获得的残余应力分别为(−127±32)、(−171±43)和(−221±55) MPa，二者吻合较好。结论 将磨轮进给率转变为等效磨削深度后，建立的多颗磨粒多次精密磨削有限元模型可以有效预测硅晶圆自旋转精密磨削的内部残余应力，为硅基集成电路薄化工艺的开发和优化提供了指导。 |
| 英文摘要: |
| Ultra-thin silicon-based integrated circuits (usually with a thickness ≤50 μm) are crucial for achieving flexibility in high-performance integrated devices and meeting the demands for advanced device packaging. Backside precision grinding is an important technical approach enabling the low-cost, large-scale production of ultra-thin silicon-based integrated circuits. However, as the thickness decreases, the mechanical strength of silicon-based devices, which are intrinsically brittle, decreases substantially, leading to increased challenges in the grinding process. Moreover, when the device thickness approaches or falls below the thickness of the active layer (approximately ~15 μm), defects and internal residual stress generated during grinding can have a significant effect on the performance and yield of ultra-thin devices. Therefore, controlling the defects and internal residual stress during the grinding process is essential for improving the fabrication technology of flexible ultra-thin silicon-based integrated circuits. Existing characterization methods make it difficult to reliably detect internal residual stress without causing damage to the sample. It is critical to conduct a thorough analysis of the internal residual stress generated during the precision grinding of ultra-thin silicon wafers and establish quantitative relationships between process parameters and internal residual stress. In this study, with the focus on precision grinding processes, local finite element models were successfully developed for both the single-grain single-pass and multi-grain multi-pass grinding on the silicon wafer through the geometric kinematic relationship between the grinding wheel and the silicon wafer. In these models, the effect of the grinding wheel feed rate on the grinding process was transformed into the effect of equivalent grinding depth. The effect of process parameters (grinding wheel speed, grinding wheel feed rate and abrasive grain size), number of abrasive grains, and grinding cycles on the surface quality and internal residual stress of silicon wafers was investigated. Self-rotating precision grinding experiments on 12-inch silicon wafers were then carried out to validate the simulation results. The findings showed that the internal residual stress on the surface of the silicon wafer after precision grinding mainly concentrated at a depth of approximately 50 nm and rapidly decreased along the depth direction. Lowering the grinding wheel feed rate and reducing the abrasive grain size effectively reduced internal residual stress and improved surface quality. Based on the simulation results, the surface and internal areas of the silicon wafer after grinding were approximated to be in an analogous biaxial compression stress state. Then, the residual stress measured with a laser confocal micro-Raman spectrometer for grinding wheel feed rates of 0.5, 0.35, and 0.2 μm/s was (−185±33), (−216±25) , and (−283±41) MPa, respectively. The residual stress obtained from the finite element simulation of multi-grain multi-pass grinding was (−127±32), (−171±43), and (−221±55) MPa, showing good agreement between the two methods. Consequently, it can be seen that the developed finite element model of multi-grain multi-pass grinding can effectively predict the internal residual stress of silicon wafers in self-rotating precision grinding by converting the grinding wheel feed rate into equivalent grinding depth. These results provide theoretical guidance for failure analysis of ultra-thin silicon wafers during precision grinding, which is very helpful for the development and optimization of thinning processes for silicon-based integrated circuits. |
| 查看全文 查看/发表评论 下载PDF阅读器 |
| 关闭 |
|
|
|
渝公网安备 50010702501715号